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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:07:13 09/23/2011 
-- Design Name: 
-- Module Name:    mulbotblk - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mulbotblk is
    Port ( PPi : in  STD_LOGIC;
           mk : in  STD_LOGIC;
           q : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
			  OP: out STD_logic);
end mulbotblk;

architecture Behavioral of mulbotblk is

begin
OP<= (mk and q) xor PPi xor cin;
Cout<=((mk and q) and PPi)xor(Cin and((mk and q) xor PPi));


end Behavioral;

